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Hardware Design Engineer (Physical Design) at Flex Logix
Mountain View, CA, US



Digital Design Engineer involved in digital and circuit design of EFLX (embedded FPGA) cores &

NMAX (Neural Network Inference) in 40nm, 28nm, 16nm,14nm, 7nm.

- Responsible for all aspects of silicon design including:

o PnR (RTL to GDS) and timing closure for EFLX/NMAX cores in different process nodes

(40nm, 28nm, 16nm)

o optimization of custom digital cell library used for Look Up Tables, DSP and

Interconnect switches for optimal performance, power and area (PPA)

o timing closure (RTL to GDS) for EFLX/NMAX cores

o Timing Verification for EFLX/NMAX cores

o EM and IR analysis of EFLX/NMAX cores

o DFT/ATPG pattern generation

o Validation (testing) of the EFLX/NMAX cores





Must have experience in at least one successfully taped out silicon design

BSEE/MSEE with 3 or more years of relevant industry experience

Must be very smart and very motivated

Must have hands-on experience in Back-End Physical Design (RTL to GDS) PnR using tools such

as Cadence Innovus or Synopsys ICC.

Preferred experience OR willing to quickly learn:

- Standard cell library development including LIB/LEF development

- Synthesis of the EFLX cores

- Scripting language such as Perl, Python

- RTL design

Must be passionate about being part of an aggressive, venture-backed startup team that is

changing chip architecture. Must be entrepreneurial, innovative problem solver and willing to

work hard.


MUST live in Silicon Valley and have US citizenship or permanent residency (“green card”), or hold a

current H1-B visa