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Hardware SOC Design Engineer (Physical /Backend Design) at Flex Logix
Mountain View, CA, US


Digital Design Engineer involved in backend design of NMAX Neural Inference SOC in 16nm,14nm.

-Responsible for all aspects of silicon design including:
oBackend assembly of SOC using NMAX IP and DDR4 memory controller, PCIe IP and timing closure for NMAX SOC cores in different process nodes (16nm, 14nm)
oGlobal clocks and Power grid for NMAX cores
oTiming closure (RTL to GDS) for NMAX cores
oTiming Verification for EFLX/NMAX cores
oEM and IR analysis of EFLX/NMAX cores
oDFT/ATPG and test requirement for NMAX core
oValidation (testing) of the EFLX/NMAX cores


Must have hands-on experience in integrating complex IP such as Memory controller/PHY and
Serial links in ASIC, SOC or COT devices in Finfet process nodes

Must have experience in at least one successfully taped out silicon design which is in high

Must have experience in Floorplanning of complex SOC or ASIC

BSEE/MSEE with 3 or more years of relevant industry experience

Must have hands-on experience in Back-End Physical Design (RTL to GDS) PnR using tools such
as Cadence Innovus or Synopsys ICC

Must be very smart and very motivated

Preferred experience OR willing to quickly learn:

-RTL design
-Global clock distribution and Power grid planning for SOC or ASIC
-Integrating DDR & Serdes PHY with package/signal-integrity constraints
-Test requirements for complex SOC including burn-in, ATPG, At-speed

Must be passionate about being part of an aggressive, venture-backed startup team that is changing chip architecture.  Must be entrepreneurial, innovative problem solver and willing to work hard

MUST live in Silicon Valley and have US citizenship or permanent residency (“green card”), or hold a current H1-B visa

Send your resumes and contact info: only apply if you are highly qualified, very smart, super-motivated and willing to work hard!