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Hardware Design Manager /Director at Flex Logix
Mountain View, CA, US


Manage a silicon design team responsible for the digital and circuit design of the NMAX Neural Inference SoC in 16nm.

-Responsible for all aspects of silicon design management including:
oBackend assembly of SOC using NMAX IP and DDR4 memory controller, PCIe IP and timing closure for NMAX SOC cores in different process nodes (16nm, 14nm)
oGlobal clocks and Power grid for NMAX cores
oTiming closure (RTL to GDS) for NMAX cores
oTiming Verification for EFLX/NMAX cores
oEM and IR analysis of EFLX/NMAX cores
oDFT/ATPG and test requirement for NMAX core
oValidation (testing) of the EFLX/NMAX cores
-Technical and people responsibility
-Work with Architecture and front-end design team as well as external Fabs, Design Services groups to support all technical interaction for a successful SoC design.


Must have managed a team of at least 5 designers and successfully taped out an ASIC or SoC which included complex IP such as High Speed
Serial Links, LPDDR/DDR Memory Links, CPU or GPU in a finfet process nodes

Must have experience in at least one successfully taped out silicon design which is in high volume

BSEE/MSEE with 5 years of relevant industry experience
Must be very smart and very motivated
Must be a hands-on technical leader

Must have hands-on experience with Cadence Virtuoso, Spice Simulations and Back-End Physical Design

Preferred experience OR willing to quickly learn:

-RTL to GDS flow
-Silicon Package and SI/PI –ability to guide Pkg Designer
-Test requirements for complex SOC including burn-in, ATPG, At-speed
-Verification of ASIC, SoC and understanding of Verification IP

Must be passionate about being part of an aggressive, venture-backed startup team that is changing chip architecture.  Must be entrepreneurial, innovative problem solver and willing to work hard.

MUST live in Silicon Valley and have US citizenship or permanent residency (“green card”), or holding a current H1-B visa